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1 of 18 rev: 032406 general description the ds1284/DS1286 watchdog timekeepers are self-contained real-time clocks, alarms, watchdog timers, and interval timers in a 28-pin jedec dip and encapsulated dip package. the DS1286 contains an embedded lithium energy source and a quartz crystal, which eliminates the need for any external circuitry. the ds1284 requires an external quartz crystal and a v bat source, which could be a lithium battery. data contained within 64 8-bit registers can be read or written in the same manner as byte-wide static ram. data is maintained in the watchdog timekeeper by intelligent control circuitry that detects the status of v cc and write protects memory when v cc is out of tolerance. the lithium energy source can maintain data and real time for over 10 years in the absence of v cc . watchdog timekeeper information includes hundredths of seconds, seconds, minutes, hours, day, date, month, and year. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap year. the ds1284/DS1286 operate in either 24-hour or 12- hour format with an am/pm indicator. the devices provide alarm windows and interval timing between 0.01 seconds and 99.99 seconds. the real-time alarm provides for preset times of up to one week. ordering information features keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years; valid leap year compensation up to 2100 watchdog timer restarts an out-of-control processor alarm function schedules real-time-related activities embedded lithium energy cell maintains time, watchdog, user ram, and alarm information programmable interrupts and square-wave outputs maintain jedec footprint all registers are individually addressable via the address and data bus accuracy is better than 1 minute/month at +25c (edip) greater than 10 years of timekeeping in the absence of v cc 50 bytes of user nv ram underwriters laboratory (ul) recognized -40c to +85c industrial temperature range option pin configurations appear at end of data sheet. part temp range voltage (v) pin-package top mark* ds1284 0c to +70c 5.0 28 dip (600 mils) ds1284 ds1284n -40c to +85c 5.0 28 dip (600 mils) ds1284 n ds1284q 0c to +70c 5.0 28 plcc ds1284q ds1284q+ 0c to +70c 5.0 28 plcc ds1284q ds1284q/t&r 0c to +70c 5.0 28 plcc/tape and reel ds1284q ds1284q+t&r 0c to +70c 5.0 28 plcc/tape and reel ds1284q ds1284qn -40c to +85c 5.0 28 plcc ds1284qn ds1284qn+ -40c to +85c 5.0 28 plcc ds1284qn ds1284qn/t&r -40c to +85c 5.0 28 plcc/tape and reel ds1284qn ds1284qn+t&r -40c to +85c 5.0 28 plcc/tape and reel ds1284qn DS1286 0c to +70c 5.0 28 edip (720 mils) DS1286 DS1286i -40c to +85c 5.0 28 edip (720 mils) DS1286 ind DS1286i+ -40c to +85c 5.0 28 edip (720 mils) DS1286 ind + denotes a lead-free/rohs-compliant package. * a ?+? anywhere on the top mark indicates a lead-free package. ds1284/DS1286 watchdog timekeepers www.maxim-ic.com
ds1284/DS1286 2 of 18 operation?read registers the ds1284/DS1286 execute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (l ow). the unique address specifi ed by the six address inputs (a0?a5) defines which of the 64 registers is to be accessed. valid data is available to the eight data output drivers within t acc (access time) after the last address input signal is stable, provided that ce and oe access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the latter occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. operation?write registers the ds1284/DS1286 are in the write mode whenever the we and ce signals are in the active-low state after the address inputs are stable. th e latter occurring falling edge of ce or we determines the start of the write cycle. the write cycle is term inated by the earlier rising edge of ce or we . all address inputs must be kept valid thro ughout the write cycle. we must return to the high state for a minimum recovery state (t wr ) before another cycle can be ini tiated. data must be valid on the data bus with sufficient data setup (t ds ) and data hold time (t dh ) with respect to the earlier rising edge of ce or we . the oe control signal should be kept inactive (high) during write cycl es to avoid bus contention. however, if the output bus has been enabled ( ce and oe active), then we will disable the outputs in t odw from its falling edge. data retention the watchdog timekeeper provides full functional capability when v cc is greater than v tp . data is maintained in the absence of v cc without any additional support circuitry. the ds1284/DS1286 constantly monitor v cc . should the supply voltage decay, the wa tchdog timekeeper automatically write protects itself, and all inputs to the registers become ?don?t care.? both inta and intb (intb) are open-drain outputs. the two interrupts and the internal clock continue to run regardless of the level of v cc . however, it is important to ensure that the pull up resistors used with the interrupt pins are never pulled up to a value greater than v cc + 0.3v. as v cc falls below the battery voltage, a power-switching circuit turns on the lithium energy source to maintain the clock and timer data functionality. also ensure that during this time (battery-bac kup mode), the voltage present at inta and intb (intb) never exceeds the battery voltage. if the active-high mode is selected for intb (intb), this pin only goes high in the presence of v cc . during power-up, when v cc rises above approximately 3.0v, the power-switching circuit connects external v cc and disconnects the v bat energy source. normal operation can resume after v cc exceeds v tp for t rec . watchdog timekeeper registers the watchdog timekeeper has 64 8-bits-wide registers that contain all the tim ekeeping, alarm, watchdog, control, and data information. the clock, calendar, alarm, and watchdog registers are memory locations that contain external (user-accessible) and internal copi es of the data. the external copies are independent of internal functions, except that they are updated periodically by the simultaneous transfer of the incremented internal copy (see figure 1). the comma nd register bits are aff ected by both internal and external functions. this register is discussed later. the 50 bytes of ram registers can only be accessed from the external address and data bus. registers 0, 1, 2, 4, 6, 8, 9, and a cont ain time-of-day and date information (see figure 2). time-of-day information is stored in binary-coded decimal (bcd). registers 3, 5, and 7 contain the time-of-day alarm information. time-of-day alar m information is stored in bcd. register b is the command re gister and information in this register is binary. regist ers c and d are the watchdog alarm registers and information stored in thes e two registers is in bcd. registers e to 3f are user bytes and can be used to cont ain data at the user?s discretion.
ds1284/DS1286 3 of 18 pin description pin dip edip plcc name function 1 1 1 inta active-low interrupt output a. this open-drain pin requires a pullup resistor for proper operation. 2, 3 ? 2, 3 x1, x2 connections for standard 32.768khz quartz crystal. the internal oscillator circuitry is designed fo r operation with a crystal having a specified load capacitance (c l ) of 6pf. the crystal is connected directly to the x1 and x2 pins. there is no need for external capacitors or resistors. for more information on crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with dallas real time clocks. 4 2, 3, 4, 21, 24, 25 4 n.c. no connection 5?10 5?10 5?10 a5?a0 address inputs 11, 12, 13, 15, 16?19 11, 12, 13, 15, 16?19 11, 12, 13, 15, 16?19 dq0, dq1, dq2, dq3, dq4?dq7 data input/output 14, 21 14 14, 21 gnd ground 20 20 20 ce active-low chip-enable input 22 22 22 oe active-low output-enable input 23 23 23 sqw square-wave output. push-pull output. high impedance when v cc is below v tp . 24 ? 24 rclr active-low ram clear. used to clear (set to logic 1) all 50 bytes of user nv ram, but does not affect the registers involved with time, alarm, and watchdog functions. to clear the ram, rclr must be forced to an input logic 0 (-0.3v to +0.8v) during battery-backup mode when v cc is not applied. the rclr function is designed to be used via human interface (shorting to ground or by switch) and not be driven with external buffers. this pin is internally pulled up and should be left floating when not in use. 25 ? 25 v bat input for any standard 3v lithium cell or other energy source. input voltage must be held between the minimum and maximum limits for proper ope ration. the supply should be connected directly to the v bat pin. a diode must not be placed in series with the battery to the v bat pin. furthermore, a diode is not necessary because reverse charging current-protection circuitry is provided internal to the device and has passed the requirements of underwriters laboratories for ul listing. this pin should be grounded but can be left floating. 26 26 26 intb (intb) active-low (active-high) interrupt output b. when the active- high state is selected (ibh = 1), an open-drain pullup transistor connected to v cc sources current when the output is active. when the active-low state is sel ected (ibh = 0), an open-drain pulldown transistor connected to ground sinks current when the output is active. if active-high output operation is selected, a pulldown resistor is required for proper operation. when active- low output operation is selected, a pullup resistor is required for proper operation. 27 27 27 we active-low write-enable input
ds1284/DS1286 4 of 18 pin dip edip plcc name function 28 28 28 v cc primary power-supply input. when voltage is applied within normal limits, the device is fully accessible and data can be written and read. when a backup supply is connected to the device and v cc is below v tp , read and writes are inhibited. however, the timekeeping function continues unaffected by the lower input voltage. figure 1. block diagram internal registers internal counters internal registers oscillator 8 40.96 50 bytes command register external registers, clock, calendar, time of day alarm a ddress decode and control power switch 4 swap pins external registers hundredths of seconds external registers watchdog alarm internal counters data i/o buffers a 0-a5 c e o e w e v cc v bat sqw i nta i ntb / (intb) 1024hz td int wd int DS1286 only 100hz 100hz DS1286 only gnd dq0?dq7 ds1284/DS1286 x1 x2 p n n v cc ibh
ds1284/DS1286 5 of 18 hundredths-of-seconds generator the hundredths-of-seconds genera tor circuit shown in the block diagram (figure 1) is a state machine that divides the incoming frequency (4096hz) by 41 fo r 24 cycles and 40 for 1 cycle. this produces a 100hz output that is slightly off during the short te rm, and is exactly correct every 250ms. the divide ratio is given by: ratio = [41 x 24 + 40 x 1] / 25 = 40.96 thus, the long-term average fre quency output is exactly 100hz. figure 2. watchdog ti mekeeper registers
ds1284/DS1286 6 of 18 time-of-day registers registers 0, 1, 2, 4, 6, 8, 9, and a cont ain time-of-day data in bcd. ten bits within these eight registers are not used and always read 0 regardless of how they are written. bits 6 and 7 in the months register (9) are binary bits. when set to logic 0, eosc (bit 7) enables the rtc oscillator. this bit is set to logic 1 as shipped from dallas semiconductor to prevent lithiu m energy consumption during storage and shipment. the user normally turns this bit on during device init ialization. however, the oscillator can be turned on and off as necessary by setti ng this bit to the appropriate level. bit 6 of this same byte controls the square- wave output (pin 23). when set to logic 0, the square-wave output pin outputs a 1024hz square-wave signal. when set to logic 1, the square-wave output pin is in a high-impedance state. bit 6 of the hours register is defined as the 12- or 24- hour select bit. when set to logic 1, the 12-hour format is selected. in the 12-hour format, bit 5 is the am/pm bit with logi c 1 being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20?23 hours). the time-of-day re gisters are updated every 0.01 seconds from the rtc, except when the te bit (bit 7 of register b) is set low or the clock oscillator is not running. the preferred method of synchronizing data access to and from the watchdog timekeeper is to access the command register by doing a write cycle to address loca tion 0b and setting the te (t ransfer enable) bit to a logic 0. doing so freezes the external time-of-day regi sters at the present recorded time, allowing access to occur without danger of simultaneous update. when the watch registers have been read or written, a second write cycle to location 0b, sett ing the te bit to a logic 1, puts the time-of-day registers back to being updated every 0.01 second. no time is lost in the rtc because the internal copy of the time-of-day register buffers is continually incremented while the external memory registers are frozen. an alternate method of reading and writing the time-o f-day registers is to ignore synchronization. however, any single read may give erroneous data as the rtc may be in the process of updating the external memory registers as data is being read. the internal copies of seconds through years are incremented and time-of-day alarm is checked during th e period that hundreds of seconds read 99 and are transferred to the external register when hundredths of seconds roll fr om 99 to 00. a way of making sure data is valid is to do multiple reads and compare. writing the registers can al so produce err oneous results for the same reasons. a way of making sure that the write cycle has caused proper update is to do read verifies and re-execute the write cycle if data is not correct. while the possibility of erroneous results from reads and write cycles has been stated, it is worth noting that the probability of an incorrect result is kept to a minimum due to the redundant structure of the watchdog timekeeper. time-of-day alarm registers registers 3, 5, and 7 contain the time-of-day alarm regist ers. bits 3, 4, 5, and 6 of register 7 always read 0 regardless of how they are written. bit 7 of registers 3, 5, and 7 are mask bits (figure 3). when all the mask bits are logic 0, a time-of-day alarm only occurs when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. an alarm is generated every day when bit 7 of register 7 is set to logic 1. similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to logic 1. when bit 7 of registers 7, 5, and 3 is set to logic 1, an alarm occurs every minut e when register 1 (seconds) rolls from 59 to 00. time-of-day alarm registers are written and read in the same format as the time-of-day registers. the time-of-day alarm flag and interrupt is always cl eared when alarm registers are read or written.
ds1284/DS1286 7 of 18 watchdog alarm registers registers c and d contain the time for the watchdog alarm. the two re gisters contain a time count from to 99.99 seconds in bcd. the value written into the wa tchdog alarm registers can be written or read in any order. any access to registers c or d causes the watchdog alarm to reinitialize and clears the watchdog flag bit and the watchdog interrupt output . when a new value is entered or the watchdog registers are read, the watchdog timer starts counti ng down from the entered value to 0. when 0 is reached, the watchdog interrupt output goes to th e active state. the watchdog timer countdown is interrupted and reinitialized back to the entered value every time either of the registers is accessed. in this manner, controlled periodic accesses to the watc hdog timer can prevent the wa tchdog alarm from ever going to an active level. if access does not occur, th e countdown alarm is repetitive. the watchdog alarm registers always read the entered value. the actual c ountdown register is intern al and is not readable. writing registers c and d to 0 disa bles the watchdog alarm feature. command register (0bh) bit #: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name: te ipsw ibh pu/lvl wam tdm waf tdf note: the initial state of these bits is not defined. bit 7: transfer enable (te). this bit when set to logic 1 allows the internal time and date counters to update the user accessible register s. when set to logic 0, the exte rnal, user-accessible time and date registers remain static when bein g read or written, while the intern al counters continue to run. the function of this bit is fu rther described in the time- of-day registers section bit 6: interrupt pin swap (ipsw). this bit directs which type of inte rrupt is present on interrupt pins inta or intb (intb). when set to logic 1, inta becomes the time-of-day alarm interrupt pin and intb (intb) becomes the watchdog interru pt pin. when bit 6 is set to logic 0, the interrupt functions are reversed such that the time-of-day alarm is output on intb (intb) and the watchdo g interrupt is output on inta . caution should be exercised when dynamically se tting this bit as the interrupts are reversed even if in an active state. bit 5: interrupt b active high/low (ibh). when bit 5 is set to logic 1, the b interrupt output sources current when active. when bit 5 is set to logic 0, the b interrupt output sinks current when active. bit 4: pulse/level output (pu/lvl). when set to logic 1, the pulse mode is selected and inta sinks current for a minimum of 3ms and then releases. output intb (intb) either sinks or sources current for a minimum of 3ms depending on the level of bit 5. the watchdog timer continues to run and waf is cleared at the end of the pulse . when set to a logic 0, both inta and intb (intb), when active, output an active low ( intb (intb) active high when ibh = 1) until the interrupt is cleared. bit 3: watchdog alarm mask (wam). when this bit is written to logic 1, the watchdog interrupt output is deactivated regard less of the state of waf. when wam is set to logic 0 and the waf bit is set to a 1, the watchdog interrupt output goes to the active state, which is determined by bits 1, 4, 5, and 6 of the command register. bit 2: time-of-day alarm mask (tdm). when this bit is written to logic 1, the time-of-day alarm- interrupt output is deactivated rega rdless of the state of tdf. when td m is set to logic 0, the time-of-day
ds1284/DS1286 8 of 18 interrupt output goes to the active state, which is determined by bits 0, 4, 5, and 6 of the command register. bit 1: watchdog alarm flag (waf). when this bit is set interna lly to logic 1, a watchdog alarm has occurred. this bit is read-only and wr iting this register has no effect on the bit. the bit is reset when any of the watchdog alarm registers are accessed. the wam bit has no effect on the operation of this bit. if pulse mode (pu/lvl = 1) is selecte d, the watchdog continues to run and the flag is internally written to 0 at the end of the pulse. the wam bit has no effect on the operation of this bit. bit 0: time-of-day alarm flag (tdf). when this bit is set internally to a logic 1, indicates that a match with the time-of-day alarm registers has occurred. this bit is read-only and writi ng this register has no effect on the bit. the time of the alarm can be determ ined by reading the time-of-day alarm registers. the bit is reset when any of the time-of-day alarm re gisters are read. the tdm bit has no effect on the operation of this bit. figure 3. time-of-day alarm mask bits register (03h) minutes (05h) hours (07h) days function 1 1 1 alarm once per minute 0 1 1 alarm when minutes match 0 0 1 alarm when hours and minutes match 0 0 0 alarm when hours, minutes, and days match
ds1284/DS1286 9 of 18 absolute maxi mum ratings voltage range on any pin relative to ground?????????????????..-0.3v to +7.0v operating temperature range commercial??????????????????????????????..0 c to +70 c industrial??????????????????????????????...-40c to +85c storage temperature range????????????????????????...-40c to +85c soldering temperature??????..?????...see ipc/jede c j-std-020 specification (note 13) stresses beyond those listed as ?absolute maxim ratings? may cause permanent da mage to the device. these are stress ratings onl y, any functional operation of the device at these or any other conditions beyond the t hose indicated in operations section of the spe cifications is no implied. exposure to absolute maximum ratings for extended periods may affect device reliability. recommended dc oper ating conditions (t a = -40c to +85c or 0c to +70c.) parameter symbol min typ max units notes power-supply voltage v cc 4.5 5.0 5.5 v 10 input logic 1 v ih 2.2 v cc + 0.3 v 10 input logic 0 v il -0.3 +0.8 v 10 v bat input voltage v bat 2.4 3.0 3.5 v 10 dc electrical characteristics ( v cc = 5v 10%, t a = -40 c to +85 c or 0c to +70c .) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a output leakage current i lo -1.0 +1.0 a i/o leakage current ce v ih v cc i lio -1.0 +1.0 a output current at 2.4v i oh -1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 3.0 7.0 ma standby current ce > v cc - 0.5 i ccs2 4.0 ma active current i cc 15 ma write-protection voltage v tp 1.088 x v bat 1.26 x v bat 1.324 x v bat v dc electrical characteristics ( v cc = 0v, v bat = 2.4v to 3.5v, t a = 0c to +70c .) parameter symbol min typ max units notes battery current ( eosc = 0) i bat +0.5 +0.6 a
ds1284/DS1286 10 of 18 capacitance (t a = +25c) parameter symbol min typ max units notes input capacitance c in 7 10 pf output capacitance c out 7 10 pf input/output capacitance c i/o 7 10 pf ac electrical characteristics (v cc = 4.5v to 5.5v, t a = -40 c to +85 c or 0c to +70c.) parameter symbol min typ max units notes read cycle time t rc 150 ns 1 address access time t acc 150 ns ce access time t co 150 ns oe access time t oe 60 ns oe or ce to output active t coe 10 ns output high-z from deselect t od 60 ns output hold from address change t oh 10 ns write cycle time t wc 150 ns write pulse width t wp 140 ns 3 address setup time t aw 0 ns write recovery time t wr 10 ns output high-z from we t odw 50 ns output active from we t oew 10 ns data setup time t ds 45 ns 4 data hold time t dh 0 ns 4,5 inta , intb pulse width t ipw 3 ms 11,12
ds1284/DS1286 11 of 18 read cycle (note 1) write cycle 1 (notes 2, 6, 7)
ds1284/DS1286 12 of 18 write cycle 2 (notes 2, 8) timing diagram: interrupt outputs pulse mode (notes 11, 12)
ds1284/DS1286 13 of 18 power-up/power-down condition parameter symbol min typ max units notes ce at v ih before power-down t pd 0 s v cc slew from 4.5v to 0v ( ce at v ih ) t f 350 s v cc slew from 0v to 4.5v ( ce at v ih ) t r 100 s ce at v ih after power-up t rec 150 ns power-down/power-up condition (t a = +25c) parameter symbol min typ max units notes expected data-retention time (DS1286) t dr 10 years 9 warning: under no circumstances are negati ve undershoots, of any amplitude, allowed when device is in battery-backup mode.
ds1284/DS1286 14 of 18 notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high-impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds or t dh are measured from the earlier of ce or we going high. 5. t dh is measured from we going high. if ce is used to terminate the write cycle, then t dh = 20ns. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a hi gh-impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high-impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high -impedance state during this period. 9. each ds1284/DS1286 is marked with a four-digit date code aabb. aa designates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined as starting at the date of manufacture. 10. all voltages are referenced to ground. 11. applies to both interrupt pins when the alarms are set to pulse. 12. interrupt output occurs within 100ns on the alarm condition existing. 13. rtc modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy s ource contained within does not exceed +85c. however, post-solder cleaning with water-washing t echniques is acceptable, provided that ultrasonic vibrations are not used to prevent crystal damage. ac test conditions output load: 100pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns
ds1284/DS1286 15 of 18 pin configurations dq0 plcc a5 a4 a3 a2 a1 a0 v bat r clr sqw o e gnd c e dq7 n.c. x2 x1 i nta v cc w e i ntb ( intb ) dq1 dq2 gnd dq3 dq4 dq5 dq6 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 ds1284 dip (600 mils) 13 27 x2 a5 a3 a2 a1 a0 dq0 dq1 gnd dq2 v cc intb ( intb ) sqw o e gnd c e dq7 dq6 dq5 dq3 dq4 1 2 3 4 5 6 7 8 9 10 11 12 14 28 26 25 24 23 22 21 20 19 18 17 15 16 x1 n.c. a4 i nt a w e v bat r clr ds1284 13 27 edip (720 mils) n.c. a5 a3 a2 a1 a0 dq0 dq1 gnd dq2 v cc w e i ntb ( intb ) n.c. n.c. sqw o e n.c. c e dq7 dq6 dq5 dq3 dq4 1 2 3 4 5 6 7 8 9 10 11 12 14 28 26 25 24 23 22 21 20 19 18 17 15 16 n.c. n.c. a4 i nt a DS1286 top view
ds1284/DS1286 16 of 18 package information (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) pkg 28-pin plcc dim min max a in. mm 0.300 bsc 7.62 b in. mm 0.442 17.68 0.462 11.73 d in. mm 0.480 12.2 0.500 12.7 d2 in. mm 0.390 9.91 0.430 10.92 e in. mm 0.090 2.29 0.120 3.05 e2 in. mm 0.390 9.91 0.430 10.92 f in. mm 0.015 0.38 0.020 0.518 h in. mm 0.100 2.54 0.020 0.518
ds1284/DS1286 17 of 18 package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) pkg 28-pin dip dim min max a in. mm 1.445 1.470 b in. mm 0.530 0.550 c in. mm 0.140 0.160 d in. mm 0.600 0.625 e in. mm 0.015 0.040 f in. mm 0.120 0.145 g in. mm 0.090 0.110 h in. mm 0.625 0.675 j in. mm 0.008 0.012 k in. mm 0.015 0.022
ds1284/DS1286 18 of 18 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) pkg 28-pin edip dim min max a in. mm 1.520 38.61 1.540 39.12 b in. mm 0.695 17.65 0.720 18.29 c in. mm 0.350 8.89 0.375 9.52` d in. mm 0.100 2.54 0.130 3.30 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.110 2.79 0.140 3.56 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53 note: pins 2, 3, 21, 24, and 25 are missing by design.

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